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LIN-Transceiver LDO
Target Data Sheet
1 1.1 * * * * * * * * * * * * * * * * * * Overview Features
TLE 6286
Single-wire transceiver, suitable for LIN protocol Transmission rate up to 20 kBaud Compatible to LIN specification Compatible to ISO 9141 functions Very low current consumption in sleep mode Control output for voltage regulator Short circuit proof to ground and battery Overtemperature protection Output voltage tolerance 2 % 200 mA output current capability Low-drop voltage Very low standby current consumption Overtemperature protection Reverse polarity protection Short-circuit proof Watchdog Wide temperature range Suitable for use in automotive electronics
P-DSO-16-4
Type TLE 6286 G
Ordering Code on request
Package P-DSO-16-4
1.2
Description
The TLE 6286 is a single-wire transceiver with a LDO. It is chip by chip integrated circuit in a P-DSO-16-4 package. It works as an interface between the protocol controller and the physical bus. The TLE 6286 is especially suitable to drive the bus line in LIN systems in automotive and industrial applications. Further it can be used in standard ISO9141 systems. In order to reduce the current consumption the TLE 6286 offers a sleep operation mode. In this mode a voltage regulator can be controlled in order to minimize the current consumption of the whole application. The on-chip voltage regulator is designed for this
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Target Data TLE 6286
application but it is also possible to use an external voltage regulator. A wake-up caused by a message on the bus enables the voltage regulator and sets the RxD output low until the device is switched to normal operation mode. The IC is based on the Smart Power Technology SPT(R) which allows bipolar and CMOS control circuitry in accordance with DMOS power devices existing on the same monolithic circuit. The TLE 6286 is designed to withstand the severe conditions of automotive applications.
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1.3
Pin Configuration (top view)
GND
1
16
GND
RD
2
15
RO
WD
3
14
INHI
VCC
4
13
VBAT
INHO
5
12
BUS
RxD
6
11
TxD
ENLIN
7
10
VS
GND
8
9
GND
P-DSO-16-4
GND RD WD VCC INHO RxD ENLIN GND
1
Leadframe
16
GND RO INHI VBAT BUS TxD VS GND
2
15
3
Chip: Voltage Regulator
14
4
13
5
12
6
Chip: Transceiver
11
7
10
8
9
P-DSO-16-4
Figure 1
Pinout
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1.4 Pin No. 1,8,9,16 2 3 4 5 6 7 10 11 12 13
Pin Definitions and Functions: Symbol GND RD WD VCC INHO RxD ENLIN VS TxD BUS VBAT Function Ground; place to cooling tabs to improve thermal behavior Reset delay; connected to ground with capacitor Window Watchdog; rising-edge triggered, for monitoring a microcontroller 5V Output; connected to GND with 22F capacitor, ESC<3 Inhibit LIN Output; to control a voltage regulator Receive Data Output; internal 30k pull up to Vs, LOW in dominat state Enable LIN Input; integrated 30k pull down, transceiver in normal operation mode when HIGH 5V Supply Input; VCC input to supply the LIN transceiver Transmit Data Input; internal 30k pull up to Vs, LOW in dominant state LIN BUS Output/Input; internal 30k pull up to Vs, LOW in dominant state Battery Supply Input; a reverse current protection diode is required, block GND with 100nF ceramic capacitor and 22F capacitor Inhibit Voltage Regulator Input; TTL compatible, low active input Reset Output; open collector output connected to the output via a resistor of 30k
14 15
INHI RO
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1.5
Functional Block Diagram
VBAT
13
5
INHO VS ENLIN
10
30 k Bus
12
Output Stage
Mode Control Driver 30 k Temp.Protection
7
11
TxD
Receiver
6
RxD
TLE 6259 G
WD
3
5
GND
Temperature Sensor
Saturation Control and Protection Circuit
Watchdog
VBAT
13
4
VCC
Control Amplifier Bandgap Reference
Buffer Reset Generator
2 15
RD RO
Adjustment
TLE 4263 G
14 1
INHI
GND
Figure 2
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Block Diagram
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Target Data TLE 6286
2
Circuit Description
The TLE 6286 is a single-wire transceiver combined with a LDO. It is a chip by chip integrated circuit in a P-DSO-16-4 package. It works as an interface between the protocol controller and the physical bus. The TLE 6286 is especially suitable to drive the bus line in LIN systems in automotive and industrial applications. Further it can be used in standard ISO9141 systems. The on-chip voltage regulator with watchdog is designed for sleep mode applications but it is also possible to use an external voltage regulator.
Start Up Power Up
Normal Mode ENLIN INHO VCC ON high high
ENLIN ENLIN low high
Stand-By
ENLIN INHO RxD VCC low high low1) ON high3)
ENLIN (VCC
high ON)
Sleep Mode ENLIN INHO VCC low floating OFF2)
1) 2) 3)
Wake Up t > tWAKE
after wake-up via bus ON when INHO not connected to INHI after start up
Figure 3 2.1
Operation Mode State Diagram
Operation Modes
In order to reduce the current consumption the TLE 6286 offers a sleep operation mode. This mode is selected by switching the enable input EN low (see figure 3, state diagram). In the sleep mode a voltage regulator can be controlled via the INH output in order to minimize the current consumption of the whole application. A wake-up caused by a message on the communication bus automatically enables the voltage regulator by switching the INH output high. In parallel the wake-up is indicated by setting the RxD output low. When entering the normal mode this wake-up flag is reset and the RxD output is released to transmit the bus data.
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Target Data TLE 6286
In case the voltage regulator control input is not connected to INH output or the microcontroller is active respectively, the TLE6286 can be set in normal operation mode without a wake-up via the communication bus. 2.2 LIN Transceiver
The LIN Transceiver has already a pull up resistor of 30k as termination implemented. There is also a diode in this path, to protect the circuit from feedback of voltages from the bus line to the power supply. To configure the TLE 6286 as a master node, an additional external termination resistor of 1k is required. To avoid reverse currents from the bus line into the battery supply line in case of an unpowered node, it is also recommended to place a diode in series to the external pull up. For small systems (low bus capacitance) the EMC performance of the system is supported by an additional capacitor of at least 1nF in the master node (see figure 6, application circuit). An capacitor of 10F at the supply voltage input VS buffers the input voltage. In combination with the required reverse polarity diode this prevents the device from detecting power down conditions in case of negative transients on the supply line. 2.3 Voltage Regulator
The control amplifier compares a reference voltage, which is kept highly accurate by resistance adjustment, to a voltage that is proportional to the output voltage and drives the base of the series transistor via a buffer. Saturation control as a function of the load current prevents any over-saturation of the power element. If the externally scaled down output voltage at the reset threshold input drops below 1.35 V, the external reset delay capacitor is discharged by the reset generator. When the voltage of the capacitor reaches the lower threshold VDRL, a reset signal occurs at the reset output and is held until the upper threshold VDU is exceeded. If the reset threshold input is connected to GND, reset is triggered at an output voltage of typ. 4.65 V. A connected microcontroller will be monitored through the watchdog logic. In case of missing pulses at pin W, the reset output is set to low. The pulse sequence time can be set in a wide range with the reset delay capacitor. The IC can be switched at the TTL-compatible, low-active inhibit input. The IC also incorporates a number of internal circuits for protection against overload, overtemperature, reverse polarity 2.4 Input Capacitor
The input capacitor CI is necessary for compensation of line influences. Using a resistor of approx. 1 in series with CI, the oscillating circuit consisting of input inductivity and input capacitance can be damped. The output capacitor is necessary for the stability of the regulating circuit. Stability is guaranteed at values 22 F and an ESR of 3 within the operating temperature range. For small tolerances of the reset delay the spread of the capacitance of the delay capacitor and its temperature coefficient should be noted.
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2.5
Reset Timing
The power-on reset delay time is defined by the charging time of an external capacitor CD which can be calculated as follows:
CD = (trd x ID,ch)/V
Definitions:CD = delay capacitor
trd = reset delay time ID,ch = charge current, typical 60 A V = VDU, typical 1.70 V VDU = upper delay switching threshold at CD for reset delay time
2.6 Watchdog Timing
The frequency of the watchdog pulses has to be higher than the minimum pulse sequence which is set by the external reset delay capacitor CD. Calculation can be done according to the formulas given in Figure 5.
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3 3.1
Electrical Characteristics Absolute Maximum Ratings Symbol Limit Values min. max. Unit Remarks
Parameter
Voltages Supply voltage Battery supply voltage Bus input voltage Bus input voltage Logic voltages at EN, TxD, RxD Input voltages at INH Output current at INH Reset output voltage Reset delay voltage Output voltage Vcc INHIBIT voltage Watchdog voltage Electrostatic discharge voltage at Vs, Bus Electrostatic discharge voltage Temperatures Junction temperature
VCC VS Vbus Vbus VI VINH IINH VR VD VQ VINH VW VESD VESD
-0.3 -0.3 -20 -20 -0.3 -0.3
6 40 32 40
V V V V V V mA V V V V V kV kV
- - - -
t<1s 0 V < VCC < 5.5 V
VCC
+ 0.3
VS
+ 0.3 1
- 0.3 - 0.3 - 0.3 - 42 - 0.3 -4 -2
42 42 7 45 6 4 2
human body model (100 pF via 1.5 k) human body model (100 pF via 1.5 k)
Tj
-40
150
C
-
Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit.
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3.2
Operating Range Symbol Limit Values min. max. 5.5 20 150 V V C
-
Parameter Supply voltage Battery Supply Voltage Junction temperature
Unit
Remarks
VCC VS Tj
4.5 6 - 40
Thermal Shutdown (junction temperature) Thermal shutdown temp. Thermal shutdown hyst. Thermal Resistances Junction ambient
TjSD
T
150 -
170 10
190 -
C K
Rthj-a
-
115
K/W
-
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3.3
Electrical Characteristics
4.5 V < VCC < 5.5 V; 6.0 V < VS < 20 V; RL = 1 k; VEN > VEN,ON; -40 C < Tj < 125 C; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values min. typ. max.
Unit Remarks
Current Consumption Current consumption Current consumption Current consumption Current consumption Current consumption Current consumption Receiver Output RxD HIGH level output current LOW level output current Bus receiver Receiver threshold voltage, recessive to dominant edge Receiver threshold voltage, dominant to recessive edge Receiver hysteresis wake-up threshold voltage
ICC IS ICC IS IS IS
0.5 0.5 0.7 0.7 20 20
1.5 1.0 2.0 1.5 30 40
mA mA mA mA A A
recessive state; VTxD = VCC recessive state; VTxD = VCC dominant state; VTxD = 0 V dominant state; VTxD = 0 V sleep mode; Tj = 25 C sleep mode
IRD,H IRD,L
-0.7 0.4 0.7
-0.4
mA mA
VRD = 0.8 x VCC, VRD = 0.2 x VCC,
Vbus,rd Vbus,dr
0.44 x VS
0.48 x VS 0.52 x VS 0.04 x VS 0.55 x VS 0.56 x VS 0.06 x VS 0.70 x VS
V V mV V
-8 V < Vbus < Vbus,dom
Vbus,rec < Vbus < 20 V
Vbus,hys 0.02 x VS Vwake 0.40 x VS
Vbus,hys = Vbus,rec - Vbus,dom
Transmission Input TxD HIGH level input voltage threshold TxD input hysteresis
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VTD,H VTD,hys
300
11
2.9 600
0.7 x
V mV
recessive state
VCC
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Target Data TLE 6286
3.3
Electrical Characteristics (cont'd)
4.5 V < VCC < 5.5 V; 6.0 V < VS < 20 V; RL = 1 k; VEN > VEN,ON; -40 C < Tj < 125 C; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified.
Parameter LOW level input voltage threshold TxD pull up current Bus transmitter
Symbol
Limit Values min. typ. max. 0.3 x 2.1
Unit Remarks V
dominant state
VTD,L
VCC
ITD
-150
-110
-80
A
VTxD < 0.3 Vcc
Bus recessive output voltage Vbus,rec
0.9 x
VS
1.5 85 -100 5 20 47 125
V V mA A A k
VTxD = VCC
VS
Bus dominant output voltage Vbus,dom 0 Bus short circuit current Leakage current
VTxD = 0 V; Vbus,short = 13.5 V VCC = 0 V, VS = 0 V, Vbus = -8 V, Tj < 85 C VCC = 0 V, VS = 0 V, Vbus = 20 V, Tj < 85 C
Ibus,sc Ibus,lk
40 -350
Bus pull up resistance Enable input (pin ENLIN) HIGH level input voltage threshold LOW level input voltage threshold EN input hysteresis EN pull down resistance Inhibit output (pin INHO) HIGH level drop voltage VINH = VS - VINH Leakage current
Rbus
20
30
VEN,on VEN,off VEN,hys REN
2.8 0.3 x 2.2
0.7 x
V V mV
normal mode
VCC
low power mode
VCC
300 15 600 30 60 k
VINH
IINH,lk
- 5.0
0.5
1.0 5.0
V A
IINH = - 0.15 mA
sleep mode; VINHO = 0 V
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3.3
Electrical Characteristics (cont'd)
4.5 V < VCC < 5.5 V; 6.0 V < VS < 20 V; RL = 1 k; VEN > VEN,ON; -40 C < Tj < 125 C; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values min. typ. max.
Unit Remarks
Vcc Output (pin Vcc) Output voltage Output voltage Output current Current consumption; Iq = II - IQ
VQ VQ IQ Iq Iq Iq Iq Vdr
VQ,lo VQ.li PSRR
4.90 4.90 200 - - - - - - - -
5.00 5.00 250 0 900 10 15 0.35 - 3 54
5.10 5.10 - 50
V V mA A
5 mA IQ 150 mA; 6 V VI 28 V 6 V VI 32 V; IQ = 100 mA; Tj = 100 C 1) VINH = 0 IQ = 0 mA IQ = 150 mA IQ = 150 mA; VI = 4.5 V
1300 A 18 mA 23 mA 0.50 25 25 - V mV mV dB
Drop voltage Load regulation Line regulation Power Supply Ripple Rejection Reset Genarator (pin RD)
IQ = 150 mA1) IQ = 5 mA to 150 mA VI = 6 V to 28 V; IQ = 150 mA fr = 100 Hz; Vr = 0.5 VPP
VQ,rt VRADJ,th Reset adjust threshold Reset low voltage VRO,l Saturation voltage VD,sat Upper timing threshold VDU Lower reset timing threshold VDRL Charge current ID,ch Reset delay time trd Reset reaction time trr
Switching threshold
4.5 1.26 - - 1.45 0.20 40 1.3 0.5
4.65 1.35 0.10 50 1.70 0.35 60 2.8 1.2
4.8 1.44 0.40 100 2.05 0.55 85 4.1 4
V V V mV V V A ms s
VQ > 3.5 V IRO = 1 mA VQ < VR,th - - - CD = 100 nF CD = 100 nF
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3.3
Electrical Characteristics (cont'd)
4.5 V < VCC < 5.5 V; 6.0 V < VS < 20 V; RL = 1 k; VEN > VEN,ON; -40 C < Tj < 125 C; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values min. typ. max.
Unit Remarks
Watchdog (pin WD) Discharge current Upper timing threshold Lower timing threshold Watchdog trigger time Inhibit Input (INHI) Switching voltage Turn-OFF voltage Input current
Note: The reset output is low within the range VQ = 1 V to VQ,rt 1) Drop voltage = Vi - VQ (measured when the output voltage has dropped 100 mV from the nominal value obtained at 6 V input)
ID,wd VDU VDWL TWI,tr
4.40 1.45 0.20 16
6.25 1.70 0.35 22.5
9.10 2.05 0.55 27
A V V ms
VD = 1.0 V - - CD = 100 nF
VINH,ON VINH,OFF IINH
3.6 - 5
- - 10
- 0.8 25
V V A
IC turned on IC turned off VINH = 5 V
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3.3
Electrical Characteristics (cont'd)
4.5 V < VCC < 5.5 V; 6.0 V < VS < 20 V; RL = 1 k; VEN > VEN,ON; -40 C < Tj < 125 C; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values min. typ. max.
Unit Remarks
Dynamic Transceiver Characteristics falling edge slew rate
Sbus(L)
-3
-2.0
-1
V/s
80% > Vbus > 20% Cbus= 3.3 nF; Tambient < 85 C; VCC = 5 V; VS = 13.5 V 20% < Vbus < 80% Cbus= 3.3 nF; VCC = 5 V; VS = 13.5 V Cbus = 3.3nF; VCC = 5 V; VS = 13.5 V CRxD = 20 pF Cbus = 3.3 nF; VCC = 5 V; VS = 13.5 V CRxD = 20 nF VCC = 5 V
rising edge slew rate
Sbus(H)
1 2
1.5 5
3 10
V/s s
Propagation delay td(L),TR TxD-to-RxD LOW (recessive to dominant) Propagation delay td(H),TR TxD-to-RxD HIGH (dominant to recessive) Propagation delay TxD LOW to bus Propagation delay TxD HIGH to bus Propagation delay bus dominant to RxD LOW Propagation delay bus recessive to RxD HIGH Receiver delay symmetry Transmitter delay symmetry Wake-up delay time
2
5
10
s
td(L),T td(H),T td(L),R td(H),R tsym,R tsym,T twake
-2 -2 30
1 1 1 1
4 4 4 4 2 2
s s s s s s s
VCC = 5 V
VCC = 5V; CRxD = 20pF VCC = 5 V; CRxD = 20 pF tsym,R = td(L),R - td(H),R tsym,T = td(L),T - td(H),T
100
200
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Target Data TLE 6286
4
Diagrams
VI
< trr
VQ VQ, rt VD VDU VDRL
dV ID, ch = dt CD
t
t
trd
VRO
trr
t
t
Power-ON Reset Overtemperature Voltage Drop at Input Undervoltage Secondary Load Bounce Spike
AET03066
Figure 4
Time Response, Watchdog with High-Frequency Clock
VW
V
t
VQ
T WD, p
t
VD VDU VDWL VRO
T WI, tr
t
t WD, L
t
T WI, tr =
(VDU - VDWL )
D, wd
C D ; T WD, p =
(VDU -VDWL ) ( D, wc + D, wd )
D, wc x D, wd
C D ; t WD, L =
(VDU - VDWL )
t CD
AED03099
D, wc
Figure 5
Version 1.02
Timing of the Watchdog FunctionReset
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Target Data TLE 6286
5
Application
Vbat LIN bus
master node
VBAT
WD
13
3
RO 15 ENLIN
7
22 F 100 nF 1 kW
12
RxD Bus INHO
6
P
TxD 11 VS 10
5
GND
100 nF
TLE 6286 G
100 nF
14
INHI
VCC
4
5V
2
RD
GND
1,8,9,16
22 F
CD 100 nF
ECU 1
slave node
VBAT
WD
13
3
RO 15 ENLIN
7
22 F 100 nF
12
RxD Bus INHO
6
P
TxD 11 VS 10
5
GND
100 nF
TLE 6286 G
100 nF
14
INHI
VCC
4
5V
2
RD
GND
1,8,9,16
22 F
CD 100 nF
ECU X
Figure 6
Application Circuit
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Target Data TLE 6286
6
Package Outlines P-DSO-16-4 (Plastic Dual Small Outline Package)
Pictures of the housing will be added in near future!
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Dimensions in mm
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Target Data TLE 6286
Edition 1999-10-12 Published by Infineon Technologies AG St.-Martin-Strasse 53 D-81541 Munchen (c) Infineon Technologies AG1999 All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
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